If the skill set matches the specified requirement please send your resume to

rsharif@juniper.net

If the skill set matches the specific requirements please send your resume to

1.Member Technical Staff-Forwarding (BSBU)

Job Description:

This position will be responsible for designing and developing software in C for a high performance networking product.

Work encompasses developing packet forwarding engine software including interaction with hardware and programming.

Requirements:

- BS/MS in computers and 5+ years experience, preferably in networking company.

- Strong development experience in Layer 2 Ethernet Switching/Routing and embedded data communication products.

- In-depth understanding of IP routing/forwarding and networking concepts.

- Experience in data path handling, low level chip programming and QOS concepts are expected.

- Exposure to Layer 2 Protocols, switching features and Storage Area Network is a plus.

- Strong C programming & Debugging skills.

- Experience with RTOS/UNIX kernel software is needed.

- Good team player with right attitude.

2.Member Technical Staff –(WABU)

WABU is developing SMP-based software for next generation WAN Acceleration platforms and Windows-based client. WABU India team is looking for senior engineering talent to research, design and implement software for the same. Responsibility includes assuming specific responsibility for researching and addressing all issues relating to the TCP/IP stack, routing protocols, TCP/IP dynamics and interaction of these devices with user/customer application protocols. It also includes providing software expertise to other networking software development problems and challenges on an as-needed basis.

Requirements:

-- BS/MS in Computer Science with 7-12 years of software product development expertise with (and an excellent understanding of) data networking protocols and their implementations.

-- Detailed knowledge of TCP/IP and routing protocols

-- Knowledge of the internals of Linux or BSD.

-- Should be fluent in software development in C/C++.

-- Experience with systems design and development in a SMP environment is a plus.

-- Familiarity with JUNOS is an asset.

3. Member Technical Staff-Interface (BSBU)

· Experience in embedded programming using C to develop device drivers.

· Experience in programming in Unix environment is a plus.

· Experienced in working on network device drivers is preferred.

· Working knowledge of debugging techniques in embedded/unix environment.

· Knowledge of LAN/WAN interfaces for enterprise is preferred.

· Knowledge of L2 protocols for WAN interfaces is a plus.

· Candidates must have a Bachelors or Masters in Computer Science with a minimum of 4 years of experience in networking.

· Candidates must have good oral and written communication skills and must be able to work well in a cross-functional team with hardware and quality assurance.

Position : ASIC Design Engineer

Experience : 6 – 12 yrs

Job Summary

• Responsible for block level/ full chip design.

Responsibilities

• Develop micro-architecture and RTL implementation for ASIC's and systems for high-performance networking products.
• Work with verification engineers to ensure first-time working silicon.
• Perform logic synthesis and timing analysis.
• Work with physical design and signal integrity teams to achieve timing closure in routed netlists.

Qualification

• Requires a BS/MS EE or equivalent and a minimum of 5+ years of ASIC design experience.
• Strong Verilog, Synopsys DC experience.
• Must have good communication skills.
• Networking experience is highly desirable, but not required.

Position : Senior ASIC Verification Engineer

Experience : 6- 12 yrs

Job Summary

• This is an ‘Individual Contributor’ role which requires the candidate to successfully complete block/chip/system level verification.

Responsibilities

• Perform ASIC verification for large, complex high-speed ASIC’s for Juniper's next generation of networking products.
• Develop detailed test plans, block and system-level test benches and verification environments; achieve complete coverage to ensure first working silicon.
• Develop functional models for System level architectural validation.
• Lead ASIC and system bring-up.
• Need to make and maintain schedule.
• Develop modeling/verification/coverage methodology.
• You will work closely with logic designers, software developers.
• Mentor junior engineers with the verification flow, strategy.

Qualification

• Requires a BS/MS EE or equivalent and a minimum of 6+ years of ASIC verification experience.
• Strong Verilog, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
• Must have good communication skills.
• Networking experience is highly desirable, but not required.